Meanwhile, back in the hardware

The addressing unit

So, with all the bits for the various address parts in place, what does it look like?

 It's a bit tricky to have the picture large enough to see, but you can download the circuit here. It's not yet in a position to be used as a component, but we'll address <ahem> that later...

Each of the blocks we've discussed is present: the programme counter (PC), the stack pointer (SP), the address register (AR), the X and Y registers, and the adder that adds the AR to X and Y.

The two multiplexers on the right hand side select one of the four blocks and supply it directly to the external address bus: whichever is selected will point to a memory address. But there is another multiplexer at the top...

That one is more subtle; it selects an eight-bit output from any one of the registers (and indeed, eight further registers which haven't yet been discussed) and passes it back to a common bus - bus_A. The register is selected by the four-bit signal sel_source. Bus_A is applied to the inputs of all the registers in the system...

Why? Because that's a way to move the contents of any register to any other register. We use the clock signal to keep things happening at the right time: when the clock is low, the output of any of the registers is stable, and one of them is routed through the multiplexer. When the clock rises, the register selected by the decoder - fed by sel_destination - latches the data from bus_A.

This works for any register, though we haven't discussed half of them yet. It's just a question of making everything look like a register.